1. Field of the Invention
The present invention relates generally to flip chip mounting of integrated circuits to circuit boards or other mounting substrates via solder bumps, and more particularly, to a chip scale package and related method for allowing integrated circuits to be directly connected to an underlying circuit board or other substrate.
2. Description of the Related Art
Flip chips are conventionally understood by those skilled in the art to designate unpackaged integrated circuit chips that have contact pads bearing solder bumps for attachment to a patterned substrate. Such flip chips are formed from integrated circuit die that are scribed from a semiconductor wafer. During processing, such semiconductor wafer has an upper active surface through which impurities are introduced, by chemical diffusion and/or implantation, to form individual transistors and other electronic components. Metallization layers are also patterned upon the upper, or active, surface of such semiconductor wafer to electrically interconnect the electrodes of the various devices formed in such semiconductor wafer. For flip chips, the upper active surface of scribed integrated circuit die are inverted, or flipped, in order to be solder connected to an underlying patterned substrate. Heating of the solder bumps to their xe2x80x9creflowxe2x80x9d temperature melts the solder, and the xe2x80x9creflowxe2x80x9d of the solder joins the flip chip electrically and mechanically with the underlying patterned support substrate. The use of solder bumps to interconnect such flip chips to underlying support substrates is disclosed, for example, within U.S. Pat. No. 5,261,593 to Casson, et al.; within U.S. Pat. No. 5,220,200 to Blanton; within U.S. Pat. No. 5,547,740 to Higdon, et al.; and within U.S. Pat. No. 5,564,617 to Degani, et al.
Unpackaged integrated circuits are essentially bare semiconductor die, and are subject to damage if mishandled during assembly. Accordingly, many manufacturers of electronic equipment are reluctant to directly attach unpackaged flip chips to circuit boards, and many of such manufacturers desire devices that are xe2x80x9cpackagedxe2x80x9d. Consequently, many integrated circuit suppliers have elected to xe2x80x9cpackagexe2x80x9d integrated circuits in a so-called xe2x80x9cchip scale packagesxe2x80x9d to overcome customer concerns about handling bare die. A xe2x80x9cchip scale packagexe2x80x9d typically designates a package that is no more than 20 percent larger than the integrated circuit die itself. Such chip scale packages provide a minimal degree of mechanical protection to the integrated circuit die and allow it to be handled more easily; customers tend to derive a sense of security knowing that they are not handling bare die. Such chip scale packages typically join the active surface of the integrated circuit to a somewhat larger substrate; electrical contacts provided on the substrate are then used to interconnect the chip scale package to the circuit board.
Often, the supporting substrate of a flip chip assembly and the associated integrated circuit will have different coefficients of thermal expansion. Such thermal stresses can fracture the solder bumps used to join the flip chip integrated circuit to the supporting substrate, causing the circuitry to fail. It is known to those in the flip chip packaging field to utilize an underfill material around the solder bumps, and between the integrated circuit and the supporting substrate, to constrain thermal expansion differences between the chip and the substrate. While the use of such underfill material serves to improves the fatigue life of the solder joints, the application of this underfill is often perceived as an expensive process that is not consistent with standard surface mount technology manufacturing processes.
Standard flip chip solder joints are typically very small (i.e., 100 micron diameter with a joined height of 70-85 microns). To be compatible with standard surface mount technology processes, the typical solder joint is composed of a 63 Sn/Pb solder, i.e., the solder bump is composed of 63% tin and 37% lead. In one known technology, 63 Sn/Pb solder is deposited onto a substrate""s solder contact pads, and high percentage Pb solder bumps are evaporated or plated onto the flip chip bond pads of the integrated circuit; however, the size of such solder bumps was typically less than 7 mils (0.007 inch). The small solder joint, and the fatigue characteristics of these flip chip solder joints, mandate the use of an underfill to minimize the strain on the solder bumps.
Many known chip scale package processes use solder bumps to join the bonding pads of the integrated circuit to the supporting substrate. These bonding pads are typically located at the outer perimeter of the integrated circuit chip. Complex integrated circuits often require in excess of one-hundred separate bonding pads in order to make the necessary power, input, and output connections between the integrated circuit and the outside world. Consequently, such bonding pads are typically disposed close to each other and place physical limitations upon the size and height of solder bumps overlying such bonding pads. While U.S. Pat. No. 5,547,740 to Higdon, et al. discloses that some of the solder bump contact pads can be redistributed internally, away from the outer perimeter of the integrated circuit, the size of such solder bumps is unchanged.
Moreover, most of the known techniques for forming chip scale packaging of integrated circuits must be practiced at the individual die level; i.e., the semiconductor wafer from which the integrated circuits are taken must first be scribed and cut into individual die before such chip scale packaging processes can be performed. These die level packaging techniques do not obtain the cost benefits of the wafer scale processing techniques. Moreover, certain integrated circuit markets, such as memory chips, are largely driven by form factor (i.e., the physical size of the packaged integrated circuit) and the cost of packaging. Yet, many of the known chip scale package techniques involve significant added cost and increase the dimensions of the packaged integrated circuit.
One of the known wafer level processing technologies used to form chip scale packages is the Mitsubishi PMEB (Plastic Molded, Extended Bump) technique; the PMEB package from Mitsubishi utilizes a redistribution technology to move solder bump pads away from the bond pads of the integrated circuit, and also performs initial solder bumping at the wafer level; however, following these steps, the Mitsubishi PMEB technique dices the components from the semiconductor wafer, encapsulates them, and then places a eutectic xe2x80x9cextended bumpxe2x80x9d onto the surface of the package. The resulting chip scale package construction is sensitive to moisture ingress and has a relatively high cost at low lead counts. In addition, the Mitsubishi PMEB package uses a 63 Sn/Pb extended solder bump (the plastic encapsulant precludes a higher solder reflow temperature) which limits the fatigue life of the extended solder bumps.
Another known wafer level technology used to form chip scale packages is the Sandia Mini Ball Grid Array technique redistributes the locations of the solder bump locations on the integrated circuit, but requires multiple metal layers because a plating process is used for solder deposition. The redistribution wiring is provided by a first layer of deposited metal that is patterned and passivated. A second layer of metal is then sputtered over the wafer to form the solder bump pads, and standard electroplating processes are used for forming standard-sized solder bumps.
Accordingly, it is an object of the present invention to provide an improved chip scale package, and a method of forming such an improved chip scale package, for flip chip integrated circuits which is consistent with standard surface mount technology manufacturing processes, and which avoids the need to add an underfill material between the integrated circuit and a supporting substrate in order to protect the solder bumps from fatigue induced by thermal coefficient differentials.
It is another object of the present invention to provide an improved chip scale package, and method for forming the same, which can be carried out at the wafer processing level, as opposed to the discrete integrated circuit die level.
Still another object of the present invention is to provide an improved chip scale package for an integrated circuit, and method for forming the same, which is relatively inexpensive to implement, and which results in a small form factor, i.e., the resulting chip scale package is not larger than the size of the original integrated circuit.
A further object of the present invention is to provide a wafer scale chip scale package which can be directly surface mounted, yet which are better protected, and easier to handle, than bare flip chip integrated circuit die.
A still further object of the present invention is to provide a wafer scale chip scale package that can be directly surface mounted to supporting substrates via solder bumping and wherein the susceptibility of such solder bumps to fatigue is reduced.
Yet another object of the present invention is to provide such a wafer scale chip scale package which minimizes the number of metallization layers applied over the integrated circuit die to facilitate solder bumping, and which permits the formation of solder bumps by processes other than plating.
These and other objects of the present invention will become more apparent to those skilled in the art as the description of the present invention proceeds.
Briefly described, and in accordance with a preferred embodiment thereof, the present invention relates to a chip scale package that includes an integrated circuit formed upon a semiconductor die having a front surface and an opposing rear surface. A group of conductive bond pads are formed upon the front surface of the integrated circuit die proximate the outer periphery thereof for making electrical interconnections to the devices formed within the integrated circuit. A patterned metal layer is formed over the front surface of the semiconductor die, defining a number of solder bump pads that are electrically coupled to the conductive bond pads of the integrated circuit die but laterally displaced from the outer periphery of the integrated circuit die. A passivation layer extends over the front surface of the semiconductor die and above the patterned metal layer; openings formed within such passivation layer expose the solder bump pads. A protective coating can extend over the rear surface of the semiconductor die for mechanical protection. Ductile solder balls, each being generally spherical and measuring at least 9 mils (0.009 inch) in diameter, are formed upon each such solder pad for allowing the resulting structure to be directly surface mounted to a circuit board or other substrate.
In the preferred embodiment of the present invention, the aforementioned ductile solder balls consist of at least 80 percent lead (Pb) by weight. While such solder balls have a higher reflow temperature, they are also less subject to mechanical fatigue. Other ductile solder ball compositions may be used, including alloys of Indium (In).
Preferably, each of the solder bump pads is disposed upon the front surface of the semiconductor die closer to the center thereof than the corresponding conductive bond pad to which each such solder bump pad is electrically coupled. This arrangement permits the solder balls to be of larger diameter without risking that such solder balls will extend over the peripheral edge of the semiconductor die, and without risking that such solder balls will abut each other. The patterned metal layer provides a plurality of redistribution traces for electrically coupling the solder bump pads to their corresponding conductive bond pads; this patterned metal layer ideally consists of a single layer of metal that simultaneously provides both the solder bump pads as well as the redistribution traces. The aforementioned passivation layer is preferably a polymer, the compound Benzocyclobutene being preferred.
Another aspect of the present invention relates to a solder-bumped semiconductor wafer construction including a semiconductor wafer containing a plurality of like integrated circuits, each of the integrated circuits including a series of conductive bond pads formed about the outer periphery thereof upon the front surface of the semiconductor wafer for making electrical interconnections to each such integrated circuit. A patterned metal layer is formed over the front surface of the semiconductor wafer above each such integrated circuit for providing a series of solder bump pads and electrically coupling the conductive bond pads of each such integrated circuit to its corresponding series of solder bump pads. The front surface of the semiconductor wafer is protected by a passivation layer that extends over the front surface of the semiconductor wafer and above each of the patterned metal layers; openings are formed in the passivation layer above each of the solder bump pads. The rear surface of the semiconductor wafer can be protected by a protective coating formed thereupon. Ductile solder balls, each having a generally spherical shape and measuring at least 9 mils (0.009 inch) in diameter, are secured to each solder bump pad on each of the integrated circuits. The resulting semiconductor wafer can then be scribed and diced to provide a number of such integrated circuits in the form of chip scale integrated circuit packages.
The present invention also relates to a method of forming a chip scale package for a flip chip integrated circuit. According to such method, a semiconductor wafer is provided containing a number of like integrated circuits, each of such integrated circuits including a series of conductive bond pads formed upon the front surface of the semiconductor wafer and arranged about the periphery of each such integrated circuit for making electrical interconnections thereto. A protective coating can be applied over the rear surface of the semiconductor wafer. A layer of metal is applied over the front surface of the semiconductor wafer, and portions of such metal layer are then selectively removed to leave a patterned metal layer over each integrated circuit. Each of the patterned metal layers provides a series of solder bump pads upon the front surface of each such integrated circuit, each such solder bump pad being electrically coupled by such patterned metal layer to a corresponding one of the solder bump pads. A passivation layer is then applied over the front surface of the semiconductor wafer and above each of the patterned metal layers to seal the front surface of each of the integrated circuits, while leaving openings in the applied passivation layer above each of the solder bump pads. Ductile solder balls are then applied to each solder bump pad, each of the ductile solder balls having a generally spherical shape and measuring at least 9 mils (0.009 inch) in diameter. The resulting semiconductor wafer is then diced to provide a number of integrated circuits in chip scale packaged form.
The passivation layer applied in the present method is preferably a polymer layer; the product Benzocyclobutene has been found to be particularly advantageous as such a polymer passivation layer.
In practicing the method of the present invention, the solder balls are caused to be highly ductile, preferably by selecting a solder ball composition consisting of at least 80 percent lead (Pb) by weight. Alternatively, a solder ball composition consisting of an alloy of Indium (In) may also be used. In the preferred embodiment of the present method, a ductile solder ball is provided above each solder bump pad by mechanically placing a pre-formed solder ball on each such solder bump pad. Solder flux is preferably applied to the solder bump pads prior to application of the ductile solder balls; the semiconductor wafer is then heated to the reflow temperature of the solder balls following application of the ductile solder balls to permanently secure the solder balls to the underlying solder bump pad.
In view of the relatively large size of such solder balls, the present method contemplates the redistribution of the solder pads away from the periphery of the integrated circuit to points located closer to the center of each integrated circuit, as compared with the original locations of the corresponding conductive bond pads of the integrated circuit. This relocation of the solder bump pads is accomplished by providing a series of redistribution traces during the step of selectively removing portions of the applied metal layer in order to electrically couple each solder bump pad to its corresponding conductive bond pad. In practicing this method, it is preferred that the same applied metal layer is patterned to form both the solder bump pads as well as the aforementioned redistribution traces.